(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a split-gate flash cell not susceptible to inadvertent reverse tunneling during programming.
(2) Description of the Related Art
Programming (writing) and erasing of memory cells is accomplished by tunneling of electrons to and from the three components of a split-gate flash memory cell, namely, the substrate, floating gate and the control gate. The transfer of electrons is affected through the intervening thin oxide layers between the components by applying different levels of voltage on the control gate and the source and drain of the cell, as is known in the art. In order to prevent inadvertent reverse tunneling, prior art teaches various methods of forming barrier oxide barriers and spacers associated with the intervening layers. These methods, however, involve extra process steps which in turn introduce product reliability problems, and added difficulties in product manufacturability. It is disclosed later in the embodiments of the present invention a process for preventing reverse tunneling in a split-gate flash memory cell without the complexities of prior art.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIG. 1. There, a MOS transistor is formed on a semiconductor substrate (10) having a first doped region (11), a second doped region (13), a channel region (15), a gate oxide (30), a floating gate (40), intergate dielectric layer (50) and control gate (60). Substrate (10) and channel region (15) have a first conductivity type, and the first (11) and second (13) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in FIG. 1, the first doped region, (11), lies within the substrate. The second doped region, (13), lies within substrate (10) and is spaced apart form the first doped region (11). Channel region (15) lies within substrate (10) and between first (11) and second (13) doped regions. Gate oxide layer (30) overlies substrate (10). Floating gate (40), to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (30) while control gate (60), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (50) therebetween.
In the structure shown in FIG. 1, control gate (60) overlaps the channel region, (17), adjacent to channel (15) under the floating gate, (40). It will be known to those skilled in the art that this structure is needed because when the cell is erased, it leaves a positive charge on the floating gate. As a result, the channel under the floating gate becomes inverted. The series MOS transistor (formed by the control gate over the channel region) is needed in order to prevent current flow from control gate to floating gate. The length of the transistor, that is the overlap of the control gate over the channel region (17) determines the cell performance.
To program the transistor shown in FIG. 1 which shows the placement of gate, source and drain voltages or Vg, Vs, and Vd, respectively, charge is transferred from substrate (10) through gate oxide (30) and is stored on floating gate (40) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed xe2x80x9conxe2x80x9d or xe2x80x9coff.xe2x80x9d xe2x80x9cReadingxe2x80x9d of the cell""s state is accomplished by applying appropriate voltages to the cell source (11) and drain (13), and to control gate (60), and then sensing the amount of charge on floating gate (40). To erase the contents of the cell, the programming process is reversed, namely, charges are removed from the floating gate by transferring them back to the substrate through the gate oxide. Electron tunneling occurs through oxide regions (33) and (53) shown in FIG. 1.
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (F-N) tunneling as is well known in prior art. During programming, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of Fowler-Nordheim tunneling. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. Of importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Inadvertent reverse tunneling, or erasure, for example, may occur if the tunnel oxide is degraded, or other barriers to reverse tunneling are not formed in a split-gate flash memory cell.
One approach to alleviate the degradation of tunnel oxide is to separate the tunneling region from the channel with a thick insulating film as taught by Ahn in U.S. Pat. Nos. 5,716,865 and 5,652,161. Another approach, as taught by Wang in U.S. Pat. No. 5,597,751 is to deposit a thick spacer oxide layer on top of the floating gate and the source/drain region to a sufficient thickness to provide electrical insulation thereinbetween.
In still a different approach, Cho, et al., in U.S. Pat. No. 5,766,988 show a method of fabricating a thin film transistor with a negatively sloped gate. According to Cho, et al., a thin film transistor may include an insulation substrate, a gate electrode formed to have a negative slope at one side thereof on the insulation substrate, an insulation film side-wall formed at the other side of the gate electrode, a gate insulation film formed on the insulation substrate, gate electrode and side-wall, a semiconductor layer formed on the gate insulation film, impurity diffusion regions selectively formed within the semiconductor layer over the gate electrode, the side-wall and the insulation substrate on the other side of the gate electrode, and a channel region formed within the semiconductor layer at the side of the gate electrode having the negative slope.
It is disclosed in the present invention a process for preventing reverse tunneling in a split-gate flash memory cell by forming reliable silicon nitride spacers between the control gate and the floating gate without some of the complexities of prior art.
It is therefore an object of this invention to provide method of forming a split-gate flash memory not susceptible to inadvertent reverse tunneling during programming.
It is another object of this invention to provide a method of forming a spacer on the negatively tapered sidewall of a floating gate in a split-gate flash memory.
It is still another object of the present invention to provide split-gate flash memory cell having a negatively sloped floating gate with a tirangularly shaped silicon nitride spacer and not susceptible to inadvertent reverse tunneling.
These objects are accomplished by providing a silicon substrate having a plurality of active and field regions defined; forming a pad oxide layer over said substrate; forming a nitride layer over said pad oxide layer; forming and patterning a first photoresist layer over said pad oxide layer to form a photoresist mask with a pattern corresponding to the floating gate of said split-gate flash memory cell; etching said nitride layer through said photoresist mask to form an opening with a tapered profile, or a tapered opening, reaching said pad oxide layer underlying said nitride layer; removing said first photoresist layer; removing said pad oxide layer exposed at the bottom of said tapered opening in said nitride layer; forming high temperature oxide (HTO) layer over said substrate including the inside walls of said tapered opening and forming a gate oxide layer at the bottom of said tapered opening; forming a first polysilicon layer over said substrate including said tapered opening; performing chemical-mechanical polishing (CMP) of said first polysilicon layer and removing said HTO layer; oxidizing said fist polysilicon layer formed in said tapered opening, thus forming poly oxide over said first polysilicon layer; performing a high selectivity nitride etch-back to form nitride spacers; forming a second polysilicon layer over said substrate; and patterning said second polysilicon layer with a second photoresist mask having control gate pattern to form a control gate to complete the forming of said split-gate flash memory cell.
These objects are further accomplished by providing a split-gate flash memory cell having a tapered floating gate with a silicon nitride spacer and not susceptible to inadvertent reverse tunneling.